How do I design a positive and negative edge triggered D-flipflop?

D

downloaderer downloaderer

New member
My problem kinda like this; when C changes from 0 to 1, the D input is equal to Q output. The output will not change as long as C=1 but when C changes from 1 to 0 the Q output is equal to the D input.

Note: This is an Asynchronous Sequential Logic
 
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